NXP Semiconductors KL25 Series - 32.1.2 Features

Timer n
Timer 1
PIT
Peripheral
load_value
PIT
Triggers
bus clock
bus
Peripheral
Iinterrupts
registers
Figure 32-1. Block diagram of the PIT
NOTE
See the chip configuration details for the number of PIT
channels used in this MCU.
32.1.2 Features
The main features of this block are:
• Ability of timers to generate DMA trigger pulses
• Ability of timers to generate interrupts
• Maskable interrupts
• Independent timeout periods for each timer
32.2 Signal description
The PIT module has no external pins.
Signal description
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
574 Freescale Semiconductor, Inc.