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NXP Semiconductors KL25 Series - Chapter 38; I2 C Address Register 1 (I2 Cx_A1)

NXP Semiconductors KL25 Series
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I2C memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4006_6000 I2C Address Register 1 (I2C0_A1) 8 R/W 00h 38.3.1/690
4006_6001 I2C Frequency Divider register (I2C0_F) 8 R/W 00h 38.3.2/691
4006_6002 I2C Control Register 1 (I2C0_C1) 8 R/W 00h 38.3.3/692
4006_6003 I2C Status register (I2C0_S) 8 R/W 80h 38.3.4/694
4006_6004 I2C Data I/O register (I2C0_D) 8 R/W 00h 38.3.5/695
4006_6005 I2C Control Register 2 (I2C0_C2) 8 R/W 00h 38.3.6/696
4006_6006 I2C Programmable Input Glitch Filter register (I2C0_FLT) 8 R/W 00h 38.3.7/697
4006_6007 I2C Range Address register (I2C0_RA) 8 R/W 00h 38.3.8/698
4006_6008 I2C SMBus Control and Status register (I2C0_SMB) 8 R/W 00h 38.3.9/699
4006_6009 I2C Address Register 2 (I2C0_A2) 8 R/W C2h
38.3.10/
701
4006_600A I2C SCL Low Timeout Register High (I2C0_SLTH) 8 R/W 00h
38.3.11/
701
4006_600B I2C SCL Low Timeout Register Low (I2C0_SLTL) 8 R/W 00h
38.3.12/
701
4006_7000 I2C Address Register 1 (I2C1_A1) 8 R/W 00h 38.3.1/690
4006_7001 I2C Frequency Divider register (I2C1_F) 8 R/W 00h 38.3.2/691
4006_7002 I2C Control Register 1 (I2C1_C1) 8 R/W 00h 38.3.3/692
4006_7003 I2C Status register (I2C1_S) 8 R/W 80h 38.3.4/694
4006_7004 I2C Data I/O register (I2C1_D) 8 R/W 00h 38.3.5/695
4006_7005 I2C Control Register 2 (I2C1_C2) 8 R/W 00h 38.3.6/696
4006_7006 I2C Programmable Input Glitch Filter register (I2C1_FLT) 8 R/W 00h 38.3.7/697
4006_7007 I2C Range Address register (I2C1_RA) 8 R/W 00h 38.3.8/698
4006_7008 I2C SMBus Control and Status register (I2C1_SMB) 8 R/W 00h 38.3.9/699
4006_7009 I2C Address Register 2 (I2C1_A2) 8 R/W C2h
38.3.10/
701
4006_700A I2C SCL Low Timeout Register High (I2C1_SLTH) 8 R/W 00h
38.3.11/
701
4006_700B I2C SCL Low Timeout Register Low (I2C1_SLTL) 8 R/W 00h
38.3.12/
701
38.3.1 I2C Address Register 1 (I2Cx_A1)
This register contains the slave address to be used by the I2C module.
Address: Base address + 0h offset
Bit 7 6 5 4 3 2 1 0
Read
AD[7:1]
0
Write
Reset
0 0 0 0 0 0 0 0
Memory map and register descriptions
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
690 Freescale Semiconductor, Inc.

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