Address-mark wakeup allows messages to contain idle characters, but requires the msb
be reserved for use in address frames. The one, or two, if UART_BDH[SBNS] = 1, logic
1s msb of an address frame clears the UART_C2[RWU] bit before the stop bits are
received and sets the UART_S1[RDRF] flag. In this case, the character with the msb set
is received even though the receiver was sleeping during most of this character time.
40.3.4 Interrupts and status flags
The UART system has three separate interrupt vectors to reduce the amount of software
needed to isolate the cause of the interrupt. One interrupt vector is associated with the
transmitter for UART_S1[TDRE] and UART_S1[TC] events. Another interrupt vector is
associated with the receiver for RDRF, IDLE, RXEDGIF, and LBKDIF events. A third
vector is used for OR, NF, FE, and PF error conditions. Each of these ten interrupt
sources can be separately masked by local interrupt enable masks. The flags can be
polled by software when the local masks are cleared to disable generation of hardware
interrupt requests.
The UART transmitter has two status flags that can optionally generate hardware
interrupt requests. Transmit data register empty (UART_S1[TDRE]) indicates when there
is room in the transmit data buffer to write another transmit character to UART_D. If the
transmit interrupt enable (UART_C2[TIE]) bit is set, a hardware interrupt is requested
when UART_S1[TDRE] is set. Transmit complete (UART_S1[TC]) indicates that the
transmitter is finished transmitting all data, preamble, and break characters and is idle
with TxD at the inactive level. This flag is often used in systems with modems to
determine when it is safe to turn off the modem. If the transmit complete interrupt enable
(UART_C2[TCIE]) bit is set, a hardware interrupt is requested when UART_S1[TC] is
set. Instead of hardware interrupts, software polling may be used to monitor the
UART_S1[TDRE] and UART_S1[TC] status flags if the corresponding UART_C2[TIE]
or UART_C2[TCIE] local interrupt masks are cleared.
When a program detects that the receive data register is full (UART_S1[RDRF] = 1), it
gets the data from the receive data register by reading UART_D. The UART_S1[RDRF]
flag is cleared by reading UARTxS1 while UART_S1[RDRF] is set and then reading
UART_D.
When polling is used, this sequence is naturally satisfied in the normal course of the user
program. If hardware interrupts are used, UARTxS1 must be read in the interrupt service
routine (ISR). Normally, this is done in the ISR anyway to check for receive errors, so the
sequence is automatically satisfied.
Chapter 40 Universal Asynchronous Receiver/Transmitter (UART1 and UART2)
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Freescale Semiconductor, Inc. 767
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