Chapter 20
Crossbar Switch Lite (AXBS-Lite)
20.1 Introduction
NOTE
For the chip-specific implementation details of this module's
instances see the chip configuration information.
This chapter provides information on the layout, configuration, and programming of the
crossbar switch. The crossbar switch connects bus masters and bus slaves using a
crossbar switch structure. This structure allows up to four bus masters to access different
bus slaves simultaneously, while providing arbitration among the bus masters when they
access the same slave.
20.1.1 Features
The crossbar switch includes these features:
• Symmetric crossbar bus switch implementation
• Allows concurrent accesses from different masters to different slaves
• 32-bit data bus
• Operation at a 1-to-1 clock frequency with the bus masters
• Programmable configuration for fixed-priority or round-robin slave port arbitration
20.2 Memory Map / Register Definition
This crossbar switch is designed for minimal gate count. It, therefore, has no memory-
mapped configuration registers.
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Freescale Semiconductor, Inc. 331
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