NXP Semiconductors KL25 Series - SPI Baud Rate Register (Spix_Br)

SPI0_C2 field descriptions (continued)
Field Description
3
BIDIROE
Bidirectional mode output enable
When bidirectional mode is enabled, because SPI pin control 0 (SPC0) is set to 1, the BIDIROE bit
determines whether the SPI data output driver is enabled to the single bidirectional SPI I/O pin. Depending
on whether the SPI is configured as a master or a slave, it uses the MOSI (MOMI) or MISO (SISO) pin,
respectively, as the single SPI data I/O pin. When SPC0 is 0, BIDIROE has no meaning or effect.
0 Output driver disabled so SPI data I/O pin acts as an input
1 SPI I/O pin enabled as an output
2
RXDMAE
Receive DMA enable
This is the enable bit for a receive DMA request. When this bit is set to 1, a receive DMA request is
asserted when both SPRF and SPE are set, and the interrupt from SPRF is disabled.
0 DMA request for receive is disabled and interrupt from SPRF is allowed
1 DMA request for receive is enabled and interrupt from SPRF is disabled
1
SPISWAI
SPI stop in wait mode
This bit is used for power conservation while the device is in wait mode.
0 SPI clocks continue to operate in wait mode
1 SPI clocks stop when the MCU enters wait mode
0
SPC0
SPI pin control 0
This bit enables bidirectional pin configurations.
0 SPI uses separate pins for data input and data output (pin mode is normal).
In master mode of operation: MISO is master in and MOSI is master out.
In slave mode of operation: MISO is slave out and MOSI is slave in.
1 SPI configured for single-wire bidirectional operation (pin mode is bidirectional).
In master mode of operation: MISO is not used by SPI; MOSI is master in when BIDIROE is 0 or
master I/O when BIDIROE is 1.
In slave mode of operation: MISO is slave in when BIDIROE is 0 or slave I/O when BIDIROE is 1;
MOSI is not used by SPI.
37.3.3 SPI baud rate register (SPIx_BR)
Use this register to set the prescaler and bit rate divisor for an SPI master. This register
may be read or written at any time.
Address: 4007_6000h base + 2h offset = 4007_6002h
Bit 7 6 5 4 3 2 1 0
Read 0
SPPR[2:0] SPR[3:0]
Write
Reset
0 0 0 0 0 0 0 0
Memory Map and Register Descriptions
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
664 Freescale Semiconductor, Inc.