NXP Semiconductors KL25 Series - ADC Configuration Register 1 (Adcx_Cfg1)

ADCx_SC1n field descriptions (continued)
Field Description
01100 When DIFF=0, AD12 is selected as input; when DIFF=1, it is reserved.
01101 When DIFF=0, AD13 is selected as input; when DIFF=1, it is reserved.
01110 When DIFF=0, AD14 is selected as input; when DIFF=1, it is reserved.
01111 When DIFF=0, AD15 is selected as input; when DIFF=1, it is reserved.
10000 When DIFF=0, AD16 is selected as input; when DIFF=1, it is reserved.
10001 When DIFF=0, AD17 is selected as input; when DIFF=1, it is reserved.
10010 When DIFF=0, AD18 is selected as input; when DIFF=1, it is reserved.
10011 When DIFF=0, AD19 is selected as input; when DIFF=1, it is reserved.
10100 When DIFF=0, AD20 is selected as input; when DIFF=1, it is reserved.
10101 When DIFF=0, AD21 is selected as input; when DIFF=1, it is reserved.
10110 When DIFF=0, AD22 is selected as input; when DIFF=1, it is reserved.
10111 When DIFF=0, AD23 is selected as input; when DIFF=1, it is reserved.
11000 Reserved.
11001 Reserved.
11010 When DIFF=0, Temp Sensor (single-ended) is selected as input; when DIFF=1, Temp Sensor
(differential) is selected as input.
11011 When DIFF=0,Bandgap (single-ended) is selected as input; when DIFF=1, Bandgap (differential)
is selected as input.
11100 Reserved.
11101 When DIFF=0,V
REFSH
is selected as input; when DIFF=1, -V
REFSH
(differential) is selected as
input. Voltage reference selected is determined by SC2[REFSEL].
11110 When DIFF=0,V
REFSL
is selected as input; when DIFF=1, it is reserved. Voltage reference
selected is determined by SC2[REFSEL].
11111 Module is disabled.
28.3.2 ADC Configuration Register 1 (ADCx_CFG1)
The configuration Register 1 (CFG1) selects the mode of operation, clock source, clock
divide, and configuration for low power or long sample time.
Address: 4003_B000h base + 8h offset = 4003_B008h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
ADLPC
ADIV
ADLSMP
MODE ADICLK
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Chapter 28 Analog-to-Digital Converter (ADC)
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Freescale Semiconductor, Inc. 465