NXP Semiconductors KL25 Series - RTC Lock Register (RTC_LR)

RTC_SR field descriptions (continued)
Field Description
0
TIF
Time Invalid Flag
The time invalid flag is set on POR or software reset. The TSR and TPR do not increment and read as
zero when this bit is set. This bit is cleared by writing the TSR register when the time counter is disabled.
0 Time is valid.
1 Time is invalid and time counter is read as zero.
34.2.7 RTC Lock Register (RTC_LR)
Address: 4003_D000h base + 18h offset = 4003_D018h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0 1
LRL SRL CRL TCL
1
W
Reset
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
RTC_LR field descriptions
Field Description
31–8
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
7
Reserved
This field is reserved.
This read-only field is reserved and always has the value 1.
6
LRL
Lock Register Lock
After being cleared, this bit can be set only by POR or software reset.
0 Lock Register is locked and writes are ignored.
1 Lock Register is not locked and writes complete as normal.
5
SRL
Status Register Lock
After being cleared, this bit can be set only by POR or software reset.
0 Status Register is locked and writes are ignored.
1 Status Register is not locked and writes complete as normal.
4
CRL
Control Register Lock
After being cleared, this bit can only be set by POR.
0 Control Register is locked and writes are ignored.
1 Control Register is not locked and writes complete as normal.
Table continues on the next page...
Register definition
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
604 Freescale Semiconductor, Inc.