RTC_LR field descriptions (continued)
Field Description
3
TCL
Time Compensation Lock
After being cleared, this bit can be set only by POR or software reset.
0 Time Compensation Register is locked and writes are ignored.
1 Time Compensation Register is not locked and writes complete as normal.
2–0
Reserved
This field is reserved.
This read-only field is reserved and always has the value 1.
34.2.8 RTC Interrupt Enable Register (RTC_IER)
Address: 4003_D000h base + 1Ch offset = 4003_D01Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
WPON
Reserved TSIE
Reserved
TAIE TOIE TIIE
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1
RTC_IER field descriptions
Field Description
31–8
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
7
WPON
Wakeup Pin On
The wakeup pin is optional and not available on all devices. Whenever the wakeup pin is enabled and this
bit is set, the wakeup pin will assert.
0 No effect.
1 If the wakeup pin is enabled, then the wakeup pin will assert.
6–5
Reserved
This field is reserved.
4
TSIE
Time Seconds Interrupt Enable
The seconds interrupt is an edge-sensitive interrupt with a dedicated interrupt vector. It is generated once
a second and requires no software overhead (there is no corresponding status flag to clear).
Table continues on the next page...
Chapter 34 Real Time Clock (RTC)
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Freescale Semiconductor, Inc. 605
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