Table 10-2. Port control register configuration summary (continued)
This field
of
PORTx_PC
Rn
Generally
resets to
Except for Resets to Configurability
ISF 0 No exceptions - all are cleared on reset. — Only implemented for
ports that support interrupt
and DMA functionality.
1. The RESET pin has the passive analog filter fixed enabled when functioning as the RESET pin (FOPT[RESET_PIN_CFG]
= 1) and fixed disabled when configured for other shared functions.
10.2.2 Clock gating
The clock to the port control module can be gated on and off using the SCGC5[PORTx]
bits in the SIM module. These bits are cleared after any reset, which disables the clock to
the corresponding module to conserve power. Prior to initializing the corresponding
module, set SCGC5[PORTx] in the SIM module to enable the clock. Before turning off
the clock, make sure to disable the module. For more details, refer to the clock
distribution chapter.
10.2.3 Signal multiplexing constraints
1. A given peripheral function must be assigned to a maximum of one package pin. Do
not program the same function to more than one pin.
2. To ensure the best signal timing for a given peripheral's interface, choose the pins in
closest proximity to each other.
Pinout
10.3.1 KL25 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
80
LQFP
64
LQFP
48
QFN
32
QFN
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7
1 1 — 1 PTE0 DISABLED PTE0 UART1_TX RTC_CLKOUT CMP0_OUT I2C1_SDA
2 2 — — PTE1 DISABLED PTE1 SPI1_MOSI UART1_RX SPI1_MISO I2C1_SCL
10.3
Chapter 10 Signal Multiplexing and Signal Descriptions
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Freescale Semiconductor, Inc. 161
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