30.4 Memory map/register definition
The DAC has registers to control analog comparator and programmable voltage divider
to perform the digital-to-analog functions.
The address of a register is the sum of a base address and an address offset. The base
address is defined at the chip level. The address offset is defined at the module level.
DAC memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4003_F000 DAC Data Low Register (DAC0_DAT0L) 8 R/W 00h 30.4.1/539
4003_F001 DAC Data High Register (DAC0_DAT0H) 8 R/W 00h 30.4.2/540
4003_F002 DAC Data Low Register (DAC0_DAT1L) 8 R/W 00h 30.4.1/539
4003_F003 DAC Data High Register (DAC0_DAT1H) 8 R/W 00h 30.4.2/540
4003_F020 DAC Status Register (DAC0_SR) 8 R/W 02h 30.4.3/540
4003_F021 DAC Control Register (DAC0_C0) 8 R/W 00h 30.4.4/541
4003_F022 DAC Control Register 1 (DAC0_C1) 8 R/W 00h 30.4.5/542
4003_F023 DAC Control Register 2 (DAC0_C2) 8 R/W 01h 30.4.6/542
30.4.1 DAC Data Low Register (DACx_DATnL)
Address: 4003_F000h base + 0h offset + (2d × i), where i=0d to 1d
Bit 7 6 5 4 3 2 1 0
Read
DATA0
Write
Reset
0 0 0 0 0 0 0 0
DACx_DATnL field descriptions
Field Description
7–0
DATA0
When the DAC buffer is not enabled, DATA[11:0] controls the output voltage based on the following
formula: V
out
= V
in
* (1 + DACDAT0[11:0])/4096
When the DAC buffer is enabled, DATA is mapped to the 16-word buffer.
Chapter 30 12-bit Digital-to-Analog Converter (DAC)
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Freescale Semiconductor, Inc. 539
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