NXP Semiconductors KL25 Series - Channel (N) Value (Tpmx_Cnv)

31.3.5 Channel (n) Value (TPMx_CnV)
These registers contain the captured LPTPM counter value for the input modes or the
match value for the output modes.
In input capture mode, any write to a CnV register is ignored.
In compare modes, writing to a CnV register latches the value into a buffer. A CnV
register is updated with the value of its write buffer according to CnV Register Update .
Address: Base address + 10h offset + (8d × i), where i=0d to 5d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
VAL
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TPMx_CnV field descriptions
Field Description
31–16
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
15–0
VAL
Channel Value
Captured LPTPM counter value of the input modes or the match value for the output modes. When writing
this field, all bytes must be written at the same time.
31.3.6 Capture and Compare Status (TPMx_STATUS)
The STATUS register contains a copy of the status flag CHnF bit (in CnSC) for each
LPTPM channel, as well as the TOF bit (in SC), for software convenience.
Each CHnF bit in STATUS is a mirror of CHnF bit in CnSC. All CHnF bits can be
checked using only one read of STATUS. All CHnF bits can be cleared by writing all
ones to STATUS.
Hardware sets the individual channel flags when an event occurs on the channel. CHF is
cleared by writing a 1 to the CHF bit. Writing a 0 to CHF has no effect.
If another event occurs between the flag setting and the write operation, the write
operation has no effect; therefore, CHF remains set indicating another event has occurred.
In this case a CHF interrupt request is not lost due to the clearing sequence for a previous
CHF.
Chapter 31 Timer/PWM Module (TPM)
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Freescale Semiconductor, Inc. 557