NXP Semiconductors KL25 Series - Chapter 9 Debug; Introduction; Debug Port Pin Descriptions

Chapter 9
Debug
9.1 Introduction
This device's debug is based on the ARM CoreSight
TM
architecture and is configured to
provide the maximum flexibility as allowed by the restrictions of the pinout and other
available resources.
It provides register and memory accessibility from the external debugger interface, basic
run/halt control plus 2 breakpoints and 2 watchpoints.
Only one debug interface is supported:
• Serial Wire Debug (SWD)
9.2 Debug Port Pin Descriptions
The debug port pins default after POR to their SWD functionality.
Table 9-1. Serial wire debug pin description
Pin Name Type Description
SWD_CLK Input Serial Wire Clock. This pin is the clock for debug logic when in the Serial
Wire Debug mode. This pin is pulled down internally.
SWD_DIO Input / Output Serial wire debug data input/output. The SWD_DIO pin is used by an
external debug tool for communication and device control. This pin is
pulled up internally.
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Freescale Semiconductor, Inc. 151