3.3.1.3 System Tick Timer
The CLKSOURCE bit in SysTick Control and Status register selects either the core clock
(when CLKSOURCE = 1) or a divide-by-16 of the core clock (when CLKSOURCE = 0).
Because the timing reference is a variable frequency, the TENMS bit in the SysTick
Calibration Value Register is always zero.
3.3.1.4 Debug Facilities
This device supports standard ARM 2-pin SWD debug port.
3.3.1.5 Core Privilege Levels
The Core on this device is implemented with both Privileged and Unprivileged levels.
The ARM documentation uses different terms than this document to distinguish between
privilege levels.
If you see this term... it also means this term...
Privileged Supervisor
Unprivileged or user User
3.3.2 Nested Vectored Interrupt Controller (NVIC) Configuration
This section summarizes how the module has been configured in the chip. Full
documentation for this module is provided by ARM and can be found at www.arm.com.
Nested Vectored
Interrupt Controller
(NVIC)
ARM Cortex-M0+
core
Interrupts
Module
Module
Module
PPB
Figure 3-2. NVIC configuration
Table 3-5. Reference links to related information
Topic Related module Reference
Full description Nested Vectored
Interrupt Controller
(NVIC)
ARM Cortex-M0+ Technical Reference Manual
Table continues on the next page...
Chapter 3 Chip Configuration
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Freescale Semiconductor, Inc. 51
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