Table 38-44. Interrupt summary
Interrupt source Status Flag Local enable
Complete 1-byte transfer TCF IICIF IICIE
Match of received calling address IAAS IICIF IICIE
Arbitration lost ARBL IICIF IICIE
I
2
C bus stop detection STOPF IICIF IICIE & STOPIE
SMBus SCL low timeout SLTF IICIF IICIE
SMBus SCL high SDA low timeout SHTF2 IICIF IICIE & SHTF2IE
Wakeup from stop or wait mode IAAS IICIF IICIE & WUEN
38.4.6.1 Byte transfer interrupt
The Transfer Complete Flag (TCF) bit is set at the falling edge of the ninth clock to
indicate the completion of a byte and acknowledgement transfer. When FACK is enabled,
TCF is then set at the falling edge of eighth clock to indicate the completion of byte.
38.4.6.2 Address detect interrupt
When the calling address matches the programmed slave address (I2C Address Register)
or when the GCAEN bit is set and a general call is received, the IAAS bit in the Status
Register is set. The CPU is interrupted, provided the IICIE bit is set. The CPU must
check the SRW bit and set its Tx mode accordingly.
38.4.6.3 Stop Detect Interrupt
When the stop status is detected on the I
2
C bus, the STOPF bit is set to 1. The CPU is
interrupted, provided the IICIE and STOPIE bits are both set to 1.
38.4.6.4 Exit from low-power/stop modes
The slave receive input detect circuit and address matching feature are still active on low
power modes (wait and stop). An asynchronous input matching slave address or general
call address brings the CPU out of low power/stop mode if the interrupt is not masked.
Therefore, TCF and IAAS both can trigger this interrupt.
Chapter 38 Inter-Integrated Circuit (I2C)
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Freescale Semiconductor, Inc. 713
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