CMPx_CR0 field descriptions (continued)
Field Description
101 5 consecutive samples must agree.
110 6 consecutive samples must agree.
111 7 consecutive samples must agree.
3
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
2
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
1–0
HYSTCTR
Comparator hard block hysteresis control
Defines the programmable hysteresis level. The hysteresis values associated with each level are device-
specific. See the Data Sheet of the device for the exact values.
00 Level 0
01 Level 1
10 Level 2
11 Level 3
29.7.2 CMP Control Register 1 (CMPx_CR1)
Address: 4007_3000h base + 1h offset = 4007_3001h
Bit 7 6 5 4 3 2 1 0
Read
SE WE TRIGM PMODE INV COS OPE EN
Write
Reset
0 0 0 0 0 0 0 0
CMPx_CR1 field descriptions
Field Description
7
SE
Sample Enable
At any given time, either SE or WE can be set. It is mandatory request to not set SE and WE both at a
given time.
0 Sampling mode is not selected.
1 Sampling mode is selected.
6
WE
Windowing Enable
At any given time, either SE or WE can be set. It is mandatory request to not set SE and WE both at a
given time.
0 Windowing mode is not selected.
1 Windowing mode is selected.
5
TRIGM
Trigger Mode Enable
CMP and DAC are configured to CMP Trigger mode when CMP_CR1[TRIGM] is set to 1. In addition, the
CMP should be enabled. If the DAC is to be used as a reference to the CMP, it should also be enabled.
Table continues on the next page...
Chapter 29 Comparator (CMP)
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Freescale Semiconductor, Inc. 515
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