NXP Semiconductors KL25 Series - Edge-Aligned PWM (EPWM) Mode

31.4.6 Edge-Aligned PWM (EPWM) Mode
The edge-aligned mode is selected when (CPWMS = 0), and (MSnB:MSnA = 1:0). The
EPWM period is determined by (MOD + 0x0001) and the pulse width (duty cycle) is
determined by CnV.
The CHnF bit is set and the channel (n) interrupt is generated (if CHnIE = 1) at the
channel (n) match (TPM counter = CnV), that is, at the end of the pulse width.
This type of PWM signal is called edge-aligned because the leading edges of all PWM
signals are aligned with the beginning of the period, which is the same for all channels
within an TPM.
period
counter overflow counter overflow counter overflow
channel (n) output
channel (n) match channel (n) match
channel (n) match
pulse
width
Figure 31-85. EPWM period and pulse width with ELSnB:ELSnA = 1:0
If (ELSnB:ELSnA = 0:0) when the counter reaches the value in the CnV register, the
CHnF bit is set and the channel (n) interrupt is generated (if CHnIE = 1), however the
channel (n) output is not controlled by TPM.
If (ELSnB:ELSnA = 1:0), then the channel (n) output is forced high at the counter
overflow (when the zero is loaded into the TPM counter), and it is forced low at the
channel (n) match (TPM counter = CnV) (see the following figure).
TOF bit
CHnF bit
CNT
channel (n) output
MOD = 0x0008
CnV = 0x0005
counter
overflow
channel (n)
match
counter
overflow
...
0 1
2
3
4
5
6
7
8
0
1
2
...
previous value
Figure 31-86. EPWM signal with ELSnB:ELSnA = 1:0
If (ELSnB:ELSnA = X:1), then the channel (n) output is forced low at the counter
overflow (when zero is loaded into the TPM counter), and it is forced high at the channel
(n) match (TPM counter = CnV) (see the following figure).
Chapter 31 Timer/PWM Module (TPM)
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Freescale Semiconductor, Inc. 567