24.5.3.3 Example 3: Moving from BLPI to FEE mode
In this example, the MCG will move through the proper operational modes from BLPI
mode at a 32 kHz MCGOUTCLK frequency running off the internal reference clock (see
previous example) to FEE mode using a 4 MHz crystal configured for a 20 MHz
MCGOUTCLK frequency. First, the code sequence will be described. Then there is a
flowchart that illustrates the sequence.
1. First, BLPI must transition to FBI mode.
a. C2 = 0x00
• C2[LP] is 0
2. Next, FBI will transition to FEE mode.
a. C2 = 0x1C
• C2[RANGE0] set to 2'b01 because the frequency of 4 MHz is within the
high frequency range.
• C2[HGO0] set to 1 to configure the crystal oscillator for high gain operation.
• C2[EREFS0] set to 1, because a crystal is being used.
b. C1 = 0x10
• C1[CLKS] set to 2'b00 to select the output of the FLL as system clock
source.
• C1[FRDIV] remain at 3'b010, or divide-by-128 for a reference of 4 MHz /
128 = 31.25 kHz.
• C1[IREFS] cleared to 0, selecting the external reference clock.
c. Loop until S[OSCINIT0] is 1, indicating the crystal selected by the C2[EREFS0]
bit has been initialized.
d. Loop until S[IREFST] is 0, indicating the external reference clock is the current
source for the reference clock.
e. Loop until S[CLKST] are 2'b00, indicating that the output of the FLL is selected
to feed MCGOUTCLK.
f. Now, with a 31.25 kHz reference frequency, a fixed DCO multiplier of 640,
MCGOUTCLK = 31.25 kHz * 640 / 1 = 20 MHz.
g. At this point, by default, the C4[DRST_DRS] bits are set to 2'b00 and
C4[DMX32] is cleared to 0. If the MCGOUTCLK frequency of 40 MHz is
desired instead, set the C4[DRST_DRS] bits to 0x01 to switch the FLL
Initialization / Application information
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
402 Freescale Semiconductor, Inc.
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