NXP Semiconductors KL25 Series - System Clock Gating Control Register 4 (SIM_SCGC4)

12.2.8 System Clock Gating Control Register 4 (SIM_SCGC4)
Address: 4004_7000h base + 1034h offset = 4004_8034h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
1 0
SPI1 SPI0
0
CMP
USBOTG
0
W
Reset
1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0 0
UART2 UART1 UART0
0
I2C1 I2C0
1 0
W
Reset
0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0
SIM_SCGC4 field descriptions
Field Description
31–28
Reserved
This field is reserved.
This read-only field is reserved and always has the value 1.
27–24
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
23
SPI1
SPI1 Clock Gate Control
This bit controls the clock gate to the SPI1 module.
0 Clock disabled
1 Clock enabled
22
SPI0
SPI0 Clock Gate Control
This bit controls the clock gate to the SPI0 module.
0 Clock disabled
1 Clock enabled
21–20
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
19
CMP
Comparator Clock Gate Control
This bit controls the clock gate to the comparator module.
0 Clock disabled
1 Clock enabled
18
USBOTG
USB Clock Gate Control
This bit controls the clock gate to the USB module.
Table continues on the next page...
Memory map and register definition
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
204 Freescale Semiconductor, Inc.