NXP Semiconductors KL25 Series - MCG Control 6 Register (MCG_C6)

MCG_C5 field descriptions (continued)
Field Description
Table 24-7. PLL External Reference Divide Factor (continued)
00100 5 01100 13 10100 21 11100 Reserve
d
00101 6 01101 14 10101 22 11101 Reserve
d
00110 7 01110 15 10110 23 11110 Reserve
d
00111 8 01111 16 10111 24 11111 Reserve
d
24.3.6 MCG Control 6 Register (MCG_C6)
Address: 4006_4000h base + 5h offset = 4006_4005h
Bit 7 6 5 4 3 2 1 0
Read
LOLIE0 PLLS CME0 VDIV0
Write
Reset
0 0 0 0 0 0 0 0
MCG_C6 field descriptions
Field Description
7
LOLIE0
Loss of Lock Interrrupt Enable
Determines if an interrupt request is made following a loss of lock indication. This bit only has an effect
when LOLS 0 is set.
0 No interrupt request is generated on loss of lock.
1 Generate an interrupt request on loss of lock.
6
PLLS
PLL Select
Controls whether the PLL or FLL output is selected as the MCG source when CLKS[1:0]=00. If the PLLS
bit is cleared and PLLCLKEN 0 is not set, the PLL is disabled in all modes. If the PLLS is set, the FLL is
disabled in all modes.
0 FLL is selected.
1
PLL is selected (PRDIV 0 need to be programmed to the correct divider to generate a PLL reference
clock in the range of 2–4 MHz prior to setting the PLLS bit).
5
CME0
Clock Monitor Enable
Enables the loss of clock monitoring circuit for the OSC0 external reference mux select. The LOCRE0 bit
will determine if a interrupt or a reset request is generated following a loss of OSC0 indication. The CME0
bit should only be set to a logic 1 when the MCG is in an operational mode that uses the external clock
(FEE, FBE, PEE, PBE, or BLPE) . Whenever the CME0 bit is set to a logic 1, the value of the RANGE0
bits in the C2 register should not be changed. CME0 bit should be set to a logic 0 before the MCG enters
Table continues on the next page...
Chapter 24 Multipurpose Clock Generator (MCG)
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Freescale Semiconductor, Inc. 377