NXP Semiconductors KL25 Series - Memory Map and Register Descriptions; Power Mode Protection Register (SMC_PMPROT)

Table 13-1. Power modes (continued)
Mode Description
VLLS3 The core clock is gated off. System clocks to other masters and bus clocks are gated off after all
stop acknowledge signals from supporting peripherals are valid. The MCU is placed in a low
leakage mode by powering down the internal logic. All system RAM contents are retained and I/O
states are held. Internal logic states are not retained.
VLLS1 The core clock is gated off. System clocks to other masters and bus clocks are gated off after all
stop acknowledge signals from supporting peripherals are valid. The MCU is placed in a low
leakage mode by powering down the internal logic and all system RAM. I/O states are held. Internal
logic states are not retained.
VLLS0 The core clock is gated off. System clocks to other masters and bus clocks are gated off after all
stop acknowledge signals from supporting peripherals are valid. The MCU is placed in a low
leakage mode by powering down the internal logic and all system RAM. I/O states are held. Internal
logic states are not retained. The 1kHz LPO clock is disabled and the power on reset (POR) circuit
can be optionally enabled using STOPCTRL[PORPO].
13.3 Memory map and register descriptions
Details follow about the registers related to the system mode controller.
Different SMC registers reset on different reset types. Each register's description provides
details. For more information about the types of reset on this chip, refer to the Reset
section details.
NOTE
The SMC registers can be written only in supervisor mode.
Write accesses in user mode are blocked and will result in a bus
error.
SMC memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4007_E000 Power Mode Protection register (SMC_PMPROT) 8 R/W 00h 13.3.1/219
4007_E001 Power Mode Control register (SMC_PMCTRL) 8 R/W 00h 13.3.2/221
4007_E002 Stop Control Register (SMC_STOPCTRL) 8 R/W 03h 13.3.3/222
4007_E003 Power Mode Status register (SMC_PMSTAT) 8 R 01h 13.3.4/223
13.3.1 Power Mode Protection register (SMC_PMPROT)
This register provides protection for entry into any low-power run or stop mode. The
enabling of the low-power run or stop mode occurs by configuring the Power Mode
Control register (PMCTRL).
Chapter 13 System Mode Controller (SMC)
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Freescale Semiconductor, Inc. 219