NXP Semiconductors KL25 Series - 2.4.1 ARM Cortex-M0+ Core Modules; 2.4.2 System Modules

2.4.1 ARM® Cortex™-M0+ Core Modules
The following core modules are available on this device.
Table 2-2. Core modules
Module Description
ARM® Cortex™-M0+ The ARM® Cortex™-M0+ is the newest member of the Cortex M Series of
processors targeting microcontroller applications focused on very cost sensitive,
deterministic, interrupt driven environments. The Cortex M0+ processor is based
on the ARMv6 Architecture and Thumb®-2 ISA and is 100% instruction set
compatible with its predecessor, the Cortex-M0 core, and upward compatible to
Cortex-M3 and M4 cores.
NVIC The ARMv6-M exception model and nested-vectored interrupt controller (NVIC)
implement a relocatable vector table supporting many external interrupts, a single
non-maskable interrupt (NMI), and priority levels.
The NVIC replaces shadow registers with equivalent system and simplified
programmability. The NVIC contains the address of the function to execute for a
particular handler. The address is fetched via the instruction port allowing parallel
register stacking and look-up. The first sixteen entries are allocated to ARM
internal sources with the others mapping to MCU-defined interrupts.
AWIC The primary function of the Asynchronous Wake-up Interrupt Controller (AWIC) is
to detect asynchronous wake-up events in stop modes and signal to clock control
logic to resume system clocking. After clock restart, the NVIC observes the
pending interrupt and performs the normal interrupt or event processing.
Single-cycle I/O Port For high-speed, single-cycle access to peripherals, the Cortex-M0+ processor
implements a dedicated single-cycle I/O port.
Debug interfaces Most of this device's debug is based on the ARM CoreSight
™
architecture. One
debug interface is supported:
• Serial Wire Debug (SWD)
2.4.2 System Modules
The following system modules are available on this device.
Table 2-3. System modules
Module Description
System integration module (SIM) The SIM includes integration logic and several module configuration settings.
System mode controller The SMC provides control and protection on entry and exit to each power mode,
control for the Power management controller (PMC), and reset entry and exit for
the complete MCU.
Power management controller (PMC) The PMC provides the user with multiple power options. Multiple modes are
supported that allow the user to optimize power consumption for the level of
functionality needed. Includes power-on-reset (POR) and integrated low voltage
detect (LVD) with reset (brownout) capability and selectable LVD trip points.
Miscellaneous control module (MCM) The MCM includes integration logic and details.
Table continues on the next page...
Module functional categories
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
40 Freescale Semiconductor, Inc.