Table 10-1. Reference links to related information (continued)
Topic Related module Reference
Clocking Clock Distribution
Register access Peripheral bus
controller
Peripheral bridge
10.2.1 Port control and interrupt module features
• 32-pin ports
NOTE
Not all pins are available on the device. See the following
section for details.
• Port A and Port D is each assigned one interrupt. For DMA requests, Port A and Port
D each have a dedicated input to the DMA MUX.
The reset state and read/write characteristics of the bit fields within the PORTx_PCRn
registers is summarized in the table below.
Table 10-2. Port control register configuration summary
This field
of
PORTx_PC
Rn
Generally
resets to
Except for Resets to Configurability
PS 1 PTA0 0 Fixed - All are read only
PE 0 PTA0 and PTA2 1 Yes - All GPIO are
configurable
DSE 0 No exceptions - all DSE are cleared on reset. — 4 pins are configurable for
High Drive (PTB0 , PTB1,
PTD6 , PTD7). All are
others are fixed for Normal
Drive and the associated
DSE bit is read only.
SRE 1 PTA3, PTA14, PTA15, PTA16, PTA17, PTB10,
PTB11, PTB16, PTB17, PTC3, PTC4, PTC5, PTC6,
PTC7, PTD4, PTD5, PTD6, PTD7
0 Fixed - All are read only
MUX 000 PTA0, PTA3 and PTA4 111 Yes - All GPIO are
configurable
PFE 0 No exceptions - all PFE are cleared on reset.
1
— The GPIO shared with
NMI_b pin is configurable.
All other GPIO is fixed and
read only.
IRQC 000 No exceptions - all are cleared on reset. — Only implemented for
ports that support interrupt
and DMA functionality.
Table continues on the next page...
Signal Multiplexing Integration
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
160 Freescale Semiconductor, Inc.
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