32.3.7 Timer Flag Register (PIT_TFLGn)
These registers hold the PIT interrupt flags.
Address: 4003_7000h base + 10Ch offset + (16d × i), where i=0d to 1d
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
0 TIF
W
w1c
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PIT_TFLGn field descriptions
Field Description
0–30
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
31
TIF
Timer Interrupt Flag
Sets to 1 at the end of the timer period. Writing 1 to this flag clears it. Writing 0 has no effect. If enabled,
or, when TCTRLn[TIE] = 1, TIF causes an interrupt request.
0 Timeout has not yet occurred.
1 Timeout has occurred.
32.4 Functional description
This section provides the functional description of the module.
32.4.1 General operation
This section gives detailed information on the internal operation of the module. Each
timer can be used to generate trigger pulses and interrupts. Each interrupt is available on
a separate interrupt line.
Functional description
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
580 Freescale Semiconductor, Inc.
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