5. In the master, read SPIx_S while SPTEF = 1, and then write to the transmit data
register (SPIx_D) to begin transfer.
37.5.2 Pseudo-Code Example
In this example, the SPI module is set up for master mode with only hardware match
interrupts enabled. The SPI runs at a maximum baud rate of bus clock divided by 2.
Clock phase and polarity are set for an active-high SPI clock where the first edge on
SPSCK occurs at the start of the first cycle of a data transfer.
SPIx_C1=0x54(%01010100)
Bit 7 SPIE = 0 Disables receive and mode fault interrupts
Bit 6 SPE = 1 Enables the SPI system
Bit 5 SPTIE = 0 Disables SPI transmit interrupts
Bit 4 MSTR = 1 Sets the SPI module as a master SPI device
Bit 3 CPOL = 0 Configures SPI clock as active-high
Bit 2 CPHA = 1 First edge on SPSCK at start of first data transfer cycle
Bit 1 SSOE = 0 Determines SS pin function when mode fault enabled
Bit 0 LSBFE = 0 SPI serial data transfers start with most significant bit
SPIx_C2 = 0x80(%10000000)
Bit 7 SPMIE = 1 SPI hardware match interrupt enabled
Bit 6 = 0 Unimplemented
Bit 5 TXDMAE = 0 DMA request disabled
Bit 4 MODFEN = 0 Disables mode fault function
Bit 3 BIDIROE = 0 SPI data I/O pin acts as input
Bit 2 RXDMAE = 0 DMA request disabled
Bit 1 SPISWAI = 0 SPI clocks operate in wait mode
Bit 0 SPC0 = 0 uses separate pins for data input and output
SPIx_BR = 0x00(%00000000)
Bit 7 = 0 Reserved
Bit 6:4 = 000 Sets prescale divisor to 1
Bit 3:0 = 0000 Sets baud rate divisor to 2
SPIx_S = 0x00(%00000000)
Bit 7 SPRF = 0 Flag is set when receive data buffer is full
Bit 6 SPMF = 0 Flag is set when SPIx_M = receive data buffer
Table continues on the next page...
Initialization/Application Information
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
684 Freescale Semiconductor, Inc.
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