NXP Semiconductors KL25 Series - Device Clock Summary

Clock name Description
Flash clock Flash memory clock. On this device it is the same as Bus
clock.
MCGIRCLK MCG output of the slow or fast internal reference clock
MCGOUTCLK MCG output of either IRC, MCGFLLCLK, MCGPLLCLK, or
MCG's external reference clock that sources the core,
system, bus, and flash clock.
MCGFLLCLK MCG output of the FLL. MCGFLLCLK or MCGPLLCLK may
clock some modules. In addition, this clock is used for
USBFS, UART0 and TPM modules.
MCGPLLCLK MCG output of the PLL. MCGFLLCLK or MCGPLLCLK may
clock some modules. In addition, this clock is used for
USBFS, UART0 and TPM modules.
OSCCLK System oscillator output of the internal oscillator or sourced
directly from EXTAL. Used as MCG external reference clock.
OSCERCLK System oscillator output sourced from OSCCLK that may
clock some on-chip modules
OSC32KCLK System oscillator 32kHz output
ERCLK32K Clock source for some modules that is chosen as
OSC32KCLK or RTC_CLKIN
LPO PMC 1kHz output
5.4.1 Device clock summary
The following table provides more information regarding the on-chip clocks.
Table 5-1. Clock Summary
Clock name Run mode
clock frequency
VLPR mode
clock frequency
Clock source Clock is disabled
when…
MCGOUTCLK Up to 100 MHz Up to 4 MHz MCG In all stop modes
except for partial stop
modes and during PLL
locking when
MCGOUTCLK derived
from PLL.
MCGFLLCLK Up to 48 MHz N/A MCG MCG clock controls do
not enable and in all
stop modes
MCGPLLCLK Up to 100 MHz N/A MCG MCG clock controls do
not enable,
in Stop mode but
PLLSTEN=0,
or in VLPS, LLS and
VLLSx modes
Core clock Up to 48 MHz Up to 4 MHz MCGOUTCLK clock
divider
In all wait and stop
modes
Table continues on the next page...
Chapter 5 Clock Distribution
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Freescale Semiconductor, Inc. 117