NXP Semiconductors KL25 Series - Page 118

Table 5-1. Clock Summary (continued)
Clock name Run mode
clock frequency
VLPR mode
clock frequency
Clock source Clock is disabled
when…
Platform clock Up to 48 MHz Up to 4 MHz MCGOUTCLK clock
divider
In all stop modes
System clock Up to 48 MHz Up to 4 MHz MCGOUTCLK clock
divider
In all stop modes and
Compute Operation
Bus clock Up to 24 MHz Up to 1 MHz
1
MCGOUTCLK clock
divider
In all stop modes
except for partial
STOP2 mode, and
Compute Operation
SWD Clock Up to 24MHz Up to 1MHz SWD_CLK pin In all stop modes
Flash clock Up to 24 MHz Up to 1 MHz in BLPE
Up to 800 kHz in BLPI
MCGOUTCLK clock
divider
In all stop modes
except for partial
STOP2 mode
Internal reference
(MCGIRCLK)
30-40 kHz Slow IRC
or 4 MHz Fast IRC
4 MHz Fast IRC only MCG MCG_C1[IRCLKEN]
cleared,
Stop/VLPS mode and
MCG_C1[IREFSTEN]
cleared, or
LLS/VLLS mode
External reference
(OSCERCLK)
Up to 48 MHz (bypass),
30-40 kHz
or
3-32 MHz (crystal)
Up to 16 MHz (bypass),
30-40 kHz (low-range
crystal)
or
3-16 MHz (high-range
crystal)
System OSC System OSC's
OSC_CR[ERCLKEN]
cleared, or
Stop mode and
OSC_CR[EREFSTEN]
cleared
or VLLS0 and oscillator
not in external clock
mode.
External reference
32kHz
(ERCLK32K)
30-40 kHz 30-40 kHz System OSC
, or RTC_CLKIN
System OSC's
OSC_CR[ERCLKEN]
cleared
and RTC's
RTC_CR[OSCE]
cleared
or VLLS0 and oscillator
not in external clock
mode.
RTC_CLKOUT RTC 1Hz,
OSCERCLK
RTC 1Hz,
OSCERCLK
RTC 1Hz,
OSCERCLK
Clock is disabled in LLS
and VLLSx modes
LPO 1 kHz 1 kHz PMC in VLLS0
TPM clock Up to 48 MHz Up to 4 MHz MCGIRCLK,
MCGPLLCLK/2,
MCGFLLCLK, or
OSCERCLK
SIM_SOPT2[TPMSRC
]=00 or selected clock
source disabled.
Table continues on the next page...
Clock definitions
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
118 Freescale Semiconductor, Inc.