NXP Semiconductors KL25 Series - UART Data Register (Uartx_D)

UARTx_C3 field descriptions (continued)
Field Description
0 OR interrupts disabled; use polling.
1 Hardware interrupt requested when OR is set.
2
NEIE
Noise Error Interrupt Enable
This bit enables the noise flag (NF) to generate hardware interrupt requests.
0 NF interrupts disabled; use polling.
1 Hardware interrupt requested when NF is set.
1
FEIE
Framing Error Interrupt Enable
This bit enables the framing error flag (FE) to generate hardware interrupt requests.
0 FE interrupts disabled; use polling.
1 Hardware interrupt requested when FE is set.
0
PEIE
Parity Error Interrupt Enable
This bit enables the parity error flag (PF) to generate hardware interrupt requests.
0 PF interrupts disabled; use polling).
1 Hardware interrupt requested when PF is set.
39.2.8 UART Data Register (UARTx_D)
This register is actually two separate registers. Reads return the contents of the read-only
receive data buffer and writes go to the write-only transmit data buffer. Reads and writes
of this register are also involved in the automatic flag clearing mechanisms for some of
the UART status flags.
Address: Base address + 7h offset
Bit 7 6 5 4 3 2 1 0
Read
R7T7 R6T6 R5T5 R4T4 R3T3 R2T2 R1T1 R0T0
Write
Reset
0 0 0 0 0 0 0 0
UARTx_D field descriptions
Field Description
7
R7T7
Read receive data buffer 7 or write transmit data buffer 7.
6
R6T6
Read receive data buffer 6 or write transmit data buffer 6.
5
R5T5
Read receive data buffer 5 or write transmit data buffer 5.
Table continues on the next page...
Register definition
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
734 Freescale Semiconductor, Inc.