NXP Semiconductors KL25 Series - Analog Channel Inputs (Adx)

In some packages, V
REFH
is connected in the package to V
DDA
and V
REFL
to V
SSA
. If
externally available, the positive reference(s) may be connected to the same potential as
V
DDA
or may be driven by an external source to a level between the minimum Ref
Voltage High and the V
DDA
potential. V
REFH
must never exceed V
DDA
. Connect the
ground references to the same voltage potential as V
SSA
.
28.2.4 Analog Channel Inputs (ADx)
The ADC module supports up to 24 single-ended analog inputs. A single-ended input is
selected for conversion through the SC1[ADCH] channel select bits when SC1n[DIFF] is
low.
28.2.5 Differential Analog Channel Inputs (DADx)
The ADC module supports up to four differential analog channel inputs. Each differential
analog input is a pair of external pins, DADPx and DADMx, referenced to each other to
provide the most accurate analog to digital readings. A differential input is selected for
conversion through SC1[ADCH] when SC1n[DIFF] is high. All DADPx inputs may be
used as single-ended inputs if SC1n[DIFF] is low. In certain MCU configurations, some
DADMx inputs may also be used as single-ended inputs if SC1n[DIFF] is low. See the
chip configuration chapter for ADC connections specific to this MCU.
28.3 Register definition
This section describes the ADC registers.
ADC memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4003_B000 ADC Status and Control Registers 1 (ADC0_SC1A) 32 R/W 0000_001Fh 28.3.1/462
4003_B004 ADC Status and Control Registers 1 (ADC0_SC1B) 32 R/W 0000_001Fh 28.3.1/462
4003_B008 ADC Configuration Register 1 (ADC0_CFG1) 32 R/W 0000_0000h 28.3.2/465
4003_B00C ADC Configuration Register 2 (ADC0_CFG2) 32 R/W 0000_0000h 28.3.3/467
4003_B010 ADC Data Result Register (ADC0_RA) 32 R 0000_0000h 28.3.4/468
4003_B014 ADC Data Result Register (ADC0_RB) 32 R 0000_0000h 28.3.4/468
4003_B018 Compare Value Registers (ADC0_CV1) 32 R/W 0000_0000h 28.3.5/469
4003_B01C Compare Value Registers (ADC0_CV2) 32 R/W 0000_0000h 28.3.5/469
Table continues on the next page...
Chapter 28 Analog-to-Digital Converter (ADC)
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Freescale Semiconductor, Inc. 461