UARTx_C5 field descriptions (continued)
Field Description
0 Receiver samples input data using the rising edge of the baud rate clock.
1 Receiver samples input data using the rising and falling edge of the baud rate clock.
0
RESYNCDIS
Resynchronization Disable
When set, disables the resynchronization of the received data word when a data one followed by data
zero transition is detected. This bit should only be changed when the receiver is disabled.
0 Resynchronization during received data word is supported
1 Resynchronization during received data word is disabled
39.3 Functional description
The UART supports full-duplex, asynchronous, NRZ serial communication and
comprises a baud rate generator, transmitter, and receiver block. The transmitter and
receiver operate independently, although they use the same baud rate generator. The
following describes each of the blocks of the UART.
39.3.1 Baud rate generation
A 13-bit modulus counter in the baud rate generator derive the baud rate for both the
receiver and the transmitter. The value from 1 to 8191 written to SBR[12:0] determines
the baud clock divisor for the asynchronous UART baud clock. The SBR bits are in the
UART baud rate registers, BDH and BDL. The baud rate clock drives the receiver, while
the transmitter is driven by the baud rate clock divided by the over sampling ratio.
Depending on the over sampling ratio, the receiver has an acquisition rate of 4 to 32
samples per bit time.
Baud rate generation is subject to two sources of error:
• Integer division of the module clock may not give the exact target frequency.
• Synchronization with the asynchronous UART baud clock can cause phase shift.
39.3.2 Transmitter functional description
This section describes the overall block diagram for the UART transmitter, as well as
specialized functions for sending break and idle characters.
Functional description
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
738 Freescale Semiconductor, Inc.
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