NXP Semiconductors KL25 Series - Freescale Semiconductor, Inc

Table 28-75. Typical conversion time (continued)
Variable Time
AverageNum 1
BCT 20 ADCK cycles
LSTAdder 0
HSCAdder 0
The resulting conversion time is generated using the parameters listed in the preceding
table. Therefore, for a bus clock and an ADCK frequency equal to 8 MHz, the resulting
conversion time is 3.75 µs.
28.4.4.6.2 Long conversion time configuration
A configuration for long ADC conversion is:
• 16-bit differential mode with the bus clock selected as the input clock source
• The input clock divide-by-8 ratio selected
• Bus frequency of 8 MHz
• Long sample time enabled
• Configured for longest adder
• High-speed conversion disabled
• Average enabled for 32 conversions
The conversion time for this conversion is calculated by using the Figure 28-62, and the
information provided in Table 28-70 through Table 28-74. The following table lists the
variables of the Figure 28-62.
Table 28-76. Typical conversion time
Variable Time
SFCAdder 3 ADCK cycles + 5 bus clock cycles
AverageNum 32
BCT 34 ADCK cycles
LSTAdder 20 ADCK cycles
HSCAdder 0
The resulting conversion time is generated using the parameters listed in the preceding
table. Therefore, for bus clock equal to 8 MHz and ADCK equal to 1 MHz, the resulting
conversion time is 57.625 µs, that is, AverageNum. This results in a total conversion time
of 1.844 ms.
28.4.4.6.3 Short conversion time configuration
A configuration for short ADC conversion is:
Chapter 28 Analog-to-Digital Converter (ADC)
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Freescale Semiconductor, Inc. 491