NXP Semiconductors KL25 Series - Counter (Tpmx_Cnt)

TPMx_SC field descriptions (continued)
Field Description
0 LPTPM counter has not overflowed.
1 LPTPM counter has overflowed.
6
TOIE
Timer Overflow Interrupt Enable
Enables LPTPM overflow interrupts.
0 Disable TOF interrupts. Use software polling or DMA request.
1 Enable TOF interrupts. An interrupt is generated when TOF equals one.
5
CPWMS
Center-aligned PWM Select
Selects CPWM mode. This mode configures the LPTPM to operate in up-down counting mode.
This field is write protected. It can be written only when the counter is disabled.
0 LPTPM counter operates in up counting mode.
1 LPTPM counter operates in up-down counting mode.
4–3
CMOD
Clock Mode Selection
Selects the LPTPM counter clock modes. When disabling the counter, this field remain set until
acknolwedged in the LPTPM clock domain.
00 LPTPM counter is disabled
01 LPTPM counter increments on every LPTPM counter clock
10 LPTPM counter increments on rising edge of LPTPM_EXTCLK synchronized to the LPTPM counter
clock
11 Reserved
2–0
PS
Prescale Factor Selection
Selects one of 8 division factors for the clock mode selected by CMOD.
This field is write protected. It can be written only when the counter is disabled.
000 Divide by 1
001 Divide by 2
010 Divide by 4
011 Divide by 8
100 Divide by 16
101 Divide by 32
110 Divide by 64
111 Divide by 128
31.3.2 Counter (TPMx_CNT)
The CNT register contains the LPTPM counter value.
Reset clears the CNT register. Writing any value to COUNT also clears the counter.
When debug is active, the LPTPM counter does not increment unless configured
otherwise.
Chapter 31 Timer/PWM Module (TPM)
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Freescale Semiconductor, Inc. 553