NOTE
The chosen clock must remain enabled if the LPTMR is to
continue operating in all required low-power modes.
LPTMR0_PSR[PCS] Prescaler/glitch filter clock
number
Chip clock
00 0 MCGIRCLK — internal reference clock
(not available in LLS and VLLS modes)
01 1 LPO — 1 kHz clock (not available in
VLLS0 mode)
10 2 ERCLK32K (not available in VLLS0
mode when using 32 kHz oscillator)
11 3 OSCERCLK — external reference clock
(not available in VLLS0 mode)
See Clock Distribution for more details on these clocks.
3.8.4 RTC configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
Signal multiplexing
Register
access
Peripheral
bridge
Module signals
Real-time clock
Figure 3-27. RTC configuration
Table 3-42. Reference links to related information
Topic Related module Reference
Full description RTC RTC
System memory map System memory map
Clocking Clock Distribution
Power management Power management
Timers
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
90 Freescale Semiconductor, Inc.
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