NXP Semiconductors KL25 Series - Chapter 14 Power Management Controller (PMC); 14.2 Features; 14.3 Low-voltage detect (LVD) system

Chapter 14
Power Management Controller (PMC)
14.1 Introduction
NOTE
For the chip-specific implementation details of this module's
instances see the chip configuration information.
The power management controller (PMC) contains the internal voltage regulator, power
on reset (POR), and low voltage detect system.
14.2 Features
The PMC features include:
• Internal voltage regulator
• Active POR providing brown-out detect
• Low-voltage detect supporting two low-voltage trip points with four warning levels
per trip point
14.3 Low-voltage detect (LVD) system
This device includes a system to guard against low-voltage conditions. This protects
memory contents and controls MCU system states during supply voltage variations. The
system is comprised of a power-on reset (POR) circuit and a LVD circuit with a user-
selectable trip voltage: high (V
LVDH
) or low (V
LVDL
). The trip voltage is selected by the
LVDSC1[LVDV] bits. The LVD is disabled upon entering VLPx, LLS, and VLLSx
modes.
Two flags are available to indicate the status of the low-voltage detect system:
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Freescale Semiconductor, Inc. 237