NXP Semiconductors KL25 Series - SOPT1 Configuration Register (SIM_SOPT1 CFG)

SIM_SOPT1 field descriptions (continued)
Field Description
19–18
OSC32KSEL
32K oscillator clock select
Selects the 32 kHz clock source (ERCLK32K) for RTC and LPTMR. This bit is reset only on POR/LVD.
00 System oscillator (OSC32KCLK)
01 Reserved
10 RTC_CLKIN
11 LPO 1kHz
17–6
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
5–0
Reserved
This field is reserved.
12.2.2 SOPT1 Configuration Register (SIM_SOPT1CFG)
NOTE
The SOPT1CFG register is reset on System Reset not VLLS.
Address: 4004_7000h base + 4h offset = 4004_7004h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
USSWE UVSWE
URWE
0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SIM_SOPT1CFG field descriptions
Field Description
31–27
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
26
USSWE
USB voltage regulator stop standby write enable
Writing one to the USSWE bit allows the SOPT1 USBSSTBY bit to be written. This register bit clears after
a write to USBSSTBY.
Table continues on the next page...
Memory map and register definition
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
194 Freescale Semiconductor, Inc.