DMA_DSR_BCRn field descriptions (continued)
Field Description
greater than 0F_FFFFh causes a configuration error when the channel starts to execute.
After being written with a value in this range, bits 23-20 of BCR read back as 1111b.
23.3.4 DMA Control Register (DMA_DCRn)
Address: 4000_8000h base + 10Ch offset + (16d × i), where i=0d to 3d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
EINT ERQ CS AA
0
Reserved
EADREQ
SINC SSIZE DINC DSIZE
0
W
START
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
SMOD DMOD
D_REQ
0
LINKCC LCH1 LCH2
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_DCRn field descriptions
Field Description
31
EINT
Enable interrupt on completion of transfer
Determines whether an interrupt is generated by completing a transfer or by the occurrence of an error
condition.
0 No interrupt is generated.
1 Interrupt signal is enabled.
30
ERQ
Enable peripheral request
CAUTION: Be careful: a collision can occur between the START bit and D_REQ when the ERQ bit is 1.
0 Peripheral request is ignored.
1 Enables peripheral request to initiate transfer. A software-initiated request (setting the START bit) is
always enabled.
Table continues on the next page...
Chapter 23 DMA Controller Module
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Freescale Semiconductor, Inc. 357
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