6.2.2.7 Stop mode acknowledge error (SACKERR)
This reset is generated if the core attempts to enter stop mode or Compute Operation, but
not all modules acknowledge stop mode within 1025 cycles of the 1 kHz LPO clock.
A module might not acknowledge the entry to stop mode if an error condition occurs. The
error can be caused by a failure of an external clock input to a module.
6.2.2.8 Software reset (SW)
The SYSRESETREQ bit in the NVIC application interrupt and reset control register can
be set to force a software reset on the device. (See ARM's NVIC documentation for the
full description of the register fields, especially the VECTKEY field requirements.)
Setting SYSRESETREQ generates a software reset request. This reset forces a system
reset of all major components except for the debug module. A software reset causes the
RCM's SRS1[SW] bit to set.
6.2.2.9 Lockup reset (LOCKUP)
The LOCKUP gives immediate indication of seriously errant kernel software. This is the
result of the core being locked because of an unrecoverable exception following the
activation of the processor’s built in system state protection hardware.
The LOCKUP condition causes a system reset and also causes the RCM's
SRS1[LOCKUP] bit to set.
6.2.2.10 MDM-AP system reset request
Set the system reset request bit in the MDM-AP control register to initiate a system reset.
This is the primary method for resets via the SWD interface. The system reset is held
until this bit is cleared.
Set the core hold reset bit in the MDM-AP control register to hold the core in reset as the
rest of the chip comes out of system reset.
6.2.3 MCU Resets
A variety of resets are generated by the MCU to reset different modules.
Chapter 6 Reset and Boot
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Freescale Semiconductor, Inc. 131
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