NXP Semiconductors KL25 Series - Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC); Platform Control Register (MCM_PLACR)

18.2.2 Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC)
PLAMC is a 16-bit read-only register identifying the presence/absence of bus master
connections to the device's crossbar switch.
Address: F000_3000h base + Ah offset = F000_300Ah
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read 0 AMC
Write
Reset
0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1
MCM_PLAMC field descriptions
Field Description
15–8
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
7–0
AMC
Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input
port.
0 A bus master connection to AXBS input port n is absent
1 A bus master connection to AXBS input port n is present
18.2.3 Platform Control Register (MCM_PLACR)
The PLACR register selects the arbitration policy for the crossbar masters and configures
the flash memory controller.
The speculation buffer and cache in the flash memory controller is configurable via
MCM_PLACR[15:10].
The speculation buffer is enabled only for instructions after reset. It is possible to have
these states for the speculation buffer:
DFCS EFDS Description
0 0 Speculation buffer is on for instruction
and off for data.
0 1 Speculation buffer is on for instruction
and on for data.
1 X Speculation buffer is off.
Chapter 18 Miscellaneous Control Module (MCM)
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Freescale Semiconductor, Inc. 293