NXP Semiconductors KL25 Series - SPI Status Register (Spix_S)

SPI0_BR field descriptions
Field Description
7
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
6–4
SPPR[2:0]
SPI baud rate prescale divisor
This 3-bit field selects one of eight divisors for the SPI baud rate prescaler. The input to this prescaler is
the bus rate clock (BUSCLK). The output of this prescaler drives the input of the SPI baud rate divider.
Refer to the description of “SPI Baud Rate Generation” for details.
000 Baud rate prescaler divisor is 1
001 Baud rate prescaler divisor is 2
010 Baud rate prescaler divisor is 3
011 Baud rate prescaler divisor is 4
100 Baud rate prescaler divisor is 5
101 Baud rate prescaler divisor is 6
110 Baud rate prescaler divisor is 7
111 Baud rate prescaler divisor is 8
3–0
SPR[3:0]
SPI baud rate divisor
This 4-bit field selects one of nine divisors for the SPI baud rate divider. The input to this divider comes
from the SPI baud rate prescaler. Refer to the description of “SPI Baud Rate Generation” for details.
0000 Baud rate divisor is 2
0001 Baud rate divisor is 4
0010 Baud rate divisor is 8
0011 Baud rate divisor is 16
0100 Baud rate divisor is 32
0101 Baud rate divisor is 64
0110 Baud rate divisor is 128
0111 Baud rate divisor is 256
1000 Baud rate divisor is 512
All others Reserved
37.3.4 SPI status register (SPIx_S)
This register contains read-only status bits. Writes have no meaning or effect.
NOTE
Bits 3 through 0 are not implemented and always read 0.
Address: 4007_6000h base + 3h offset = 4007_6003h
Bit 7 6 5 4 3 2 1 0
Read SPRF SPMF SPTEF MODF 0
Write
Reset
0 0 1 0 0 0 0 0
Chapter 37 Serial Peripheral Interface (SPI)
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Freescale Semiconductor, Inc. 665