NXP Semiconductors KL25 Series - Timer Control Register (Pit_Tctrln)

32.3.6 Timer Control Register (PIT_TCTRLn)
These register contain the control bits for each timer.
Address: 4003_7000h base + 108h offset + (16d × i), where i=0d to 1d
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
0
CHN TIE TEN
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PIT_TCTRLn field descriptions
Field Description
0–28
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
29
CHN
Chain Mode
When activated, Timer n-1 needs to expire before timer n can decrement by 1.
Timer 0 can not be changed.
0 Timer is not chained.
1 Timer is chained to previous timer. For example, for Channel 2, if this field is set, Timer 2 is chained to
Timer 1.
30
TIE
Timer Interrupt Enable
When an interrupt is pending, or, TFLGn[TIF] is set, enabling the interrupt will immediately cause an
interrupt event. To avoid this, the associated TFLGn[TIF] must be cleared first.
0 Interrupt requests from Timer n are disabled.
1 Interrupt will be requested whenever TIF is set.
31
TEN
Timer Enable
Enables or disables the timer.
0 Timer n is disabled.
1 Timer n is enabled.
Chapter 32 Periodic Interrupt Timer (PIT)
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Freescale Semiconductor, Inc. 579