is provided from the LPTMR. The LPTMR triggering output is always enabled when the
LPTMR is enabled. The first signal is supplied to enable the CMP and DAC and is
asserted at the same time as the TCF flag is set. The delay to the second signal that
triggers the CMP to capture the result of the compare operation is dependent on the
LPTMR configuration. In Time Counter mode with prescaler enabled, the delay is 1/2
Prescaler output period. In Time Counter mode with prescaler bypassed, the delay is 1/2
Prescaler clock period.
The delay between the first signal from LPTMR and the second signal from LPTMR
must be greater than the Analog comparator initialization delay as defined in the device
datasheet.
3.7.3 12-bit DAC Configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
Signal multiplexing
Module signals
Register
access
12-bit DAC
Peripheral bus
controller 0
Other peripherals
Figure 3-23. 12-bit DAC configuration
Table 3-35. Reference links to related information
Topic Related module Reference
Full description 12-bit DAC 12-bit DAC
System memory map System memory map
Clocking Clock distribution
Power management Power management
Signal multiplexing Port control Signal multiplexing
3.7.3.1 12-bit DAC Instantiation Information
This device contains one 12-bit digital-to-analog converter (DAC) with programmable
reference generator output. The DAC includes a two word FIFO for DMA support.
Chapter 3 Chip Configuration
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Freescale Semiconductor, Inc. 83
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