NXP Semiconductors KL25 Series - ADC Minus-Side General Calibration Value Register (Adcx_Clm4)

28.3.20 ADC Minus-Side General Calibration Value Register
(ADCx_CLM4)
For more information, see CLMD register description.
Address: 4003_B000h base + 5Ch offset = 4003_B05Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
CLM4
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
ADCx_CLM4 field descriptions
Field Description
31–10
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
9–0
CLM4
Calibration Value
28.3.21 ADC Minus-Side General Calibration Value Register
(ADCx_CLM3)
For more information, see CLMD register description.
Address: 4003_B000h base + 60h offset = 4003_B060h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
CLM3
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
ADCx_CLM3 field descriptions
Field Description
31–9
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
8–0
CLM3
Calibration Value
Register definition
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
480 Freescale Semiconductor, Inc.