NXP Semiconductors KL25 Series - Functional Description

TPMx_CONF field descriptions (continued)
Field Description
Configures the LPTPM behavior in debug mode. All other configurations are reserved.
00 LPTPM counter is paused and does not increment during debug mode. Trigger inputs and input
capture events are also ignored.
11 LPTPM counter continues in debug mode.
5
DOZEEN
Doze Enable
Configures the LPTPM behavior in wait mode.
0 Internal LPTPM counter continues in Doze mode.
1 Internal LPTPM counter is paused and does not increment during Doze mode. Trigger inputs and
input capture events are also ignored.
4–0
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
31.4 Functional Description
The following sections describe the TPM features.
31.4.1 Clock Domains
The TPM module supports two clock domains.
The bus clock domain is used by the register interface and for synchronizing interrupts
and DMA requests.
The TPM counter clock domain is used to clock the counter and prescaler along with the
output compare and input capture logic. The TPM counter clock is considered
asynchronous to the bus clock, can be a higher or lower frequency than the bus clock and
can remain operational in Stop mode. Multiple TPM instances are all clocked by the
same TPM counter clock in support of the external timebase feature.
31.4.1.1 Counter Clock Mode
The CMOD[1:0] bits in the SC register either disable the TPM counter or select one of
two possible clock modes for the TPM counter. After any reset, CMOD[1:0] = 0:0 so the
TPM counter is disabled.
Chapter 31 Timer/PWM Module (TPM)
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Freescale Semiconductor, Inc. 561