80
LQFP
64
LQFP
48
QFN
32
QFN
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7
71 — — — PTC16 DISABLED PTC16
72 — — — PTC17 DISABLED PTC17
73 57 41 — PTD0 DISABLED PTD0 SPI0_PCS0 TPM0_CH0
74 58 42 — PTD1 ADC0_SE5b ADC0_SE5b PTD1 SPI0_SCK TPM0_CH1
75 59 43 — PTD2 DISABLED PTD2 SPI0_MOSI UART2_RX TPM0_CH2 SPI0_MISO
76 60 44 — PTD3 DISABLED PTD3 SPI0_MISO UART2_TX TPM0_CH3 SPI0_MOSI
77 61 45 29 PTD4/
LLWU_P14
DISABLED PTD4/
LLWU_P14
SPI1_PCS0 UART2_RX TPM0_CH4
78 62 46 30 PTD5 ADC0_SE6b ADC0_SE6b PTD5 SPI1_SCK UART2_TX TPM0_CH5
79 63 47 31 PTD6/
LLWU_P15
ADC0_SE7b ADC0_SE7b PTD6/
LLWU_P15
SPI1_MOSI UART0_RX SPI1_MISO
80 64 48 32 PTD7 DISABLED PTD7 SPI1_MISO UART0_TX SPI1_MOSI
10.3.2 KL25 Pinouts
The below figures show the pinout diagrams for the devices supported by this document.
Many signals may be multiplexed onto a single pin. To determine what signals can be
used on which pin, see the previous section.
Pinout
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
164 Freescale Semiconductor, Inc.
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