NXP Semiconductors KL25 Series - System Clock Gating Control Register 7 (SIM_SCGC7)

SIM_SCGC6 field descriptions (continued)
Field Description
14–2
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
1
DMAMUX
DMA Mux Clock Gate Control
This bit controls the clock gate to the DMA Mux module.
0 Clock disabled
1 Clock enabled
0
FTF
Flash Memory Clock Gate Control
This bit controls the clock gate to the flash memory. Flash reads are still supported while the flash memory
is clock gated, but entry into low power modes is blocked.
0 Clock disabled
1 Clock enabled
12.2.11 System Clock Gating Control Register 7 (SIM_SCGC7)
Address: 4004_7000h base + 1040h offset = 4004_8040h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
DMA
0
W
Reset
0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
SIM_SCGC7 field descriptions
Field Description
31–9
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
8
DMA
DMA Clock Gate Control
This bit controls the clock gate to the DMA module.
0 Clock disabled
1 Clock enabled
7–0
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
Chapter 12 System integration module (SIM)
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Freescale Semiconductor, Inc. 209