DMA_SARn field descriptions
Field Description
31–0
SAR
Each SAR contains the byte address used by the DMA controller to read data. The SARn is typically
aligned on a 0-modulo-ssize boundary—that is, on the natural alignment of the source data.
Restriction: Bits 31-20 of this register must be written with one of only four allowed values. Each of
these four allowed values corresponds to a valid region of the device's memory map. The
allowed values are:
• 0x000x_xxxx
• 0x1FFx_xxxx
• 0x200x_xxxx
• 0x400x_xxxx
After being written with one of the allowed values, bits 31-20 read back as the written value.
After being written with any other value, bits 31-20 read back as an indeterminate value.
23.3.2 Destination Address Register (DMA_DARn)
Restriction
For this register:
• Only 32-bit writes are allowed. 16-bit and 8-bit writes
result in a bus error.
• Only four values are allowed to be written to bits 31-20 of
this register. A write of any other value to these bits causes
a configuration error when the channel starts to execute.
For more information about the configuration error, see the
description of the CE field of DSR.
Address: 4000_8000h base + 104h offset + (16d × i), where i=0d to 3d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
DAR
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_DARn field descriptions
Field Description
31–0
DAR
Each DAR contains the byte address used by the DMA controller to write data. The DARn is typically
aligned on a 0-modulo-dsize boundary—that is, on the natural alignment of the destination data.
Restriction: Bits 31-20 of this register must be written with one of only four allowed values. Each of
these four allowed values corresponds to a valid region of the device's memory map. The
allowed values are:
• 0x000x_xxxx
• 0x1FFx_xxxx
• 0x200x_xxxx
• 0x400x_xxxx
Memory Map and Registers
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
354 Freescale Semiconductor, Inc.
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