6.2.1 Power-on reset (POR)
When power is initially applied to the MCU or when the supply voltage drops below the
power-on reset re-arm voltage level (V
POR
), the POR circuit causes a POR reset
condition.
As the supply voltage rises, the LVD circuit holds the MCU in reset until the supply has
risen above the LVD low threshold (V
LVDL
). The POR and LVD bits in reset status
register are set following a POR.
6.2.2 System reset sources
Resetting the MCU provides a way to start processing from a known set of initial
conditions. System reset begins with the on-chip regulator in full regulation and system
clocking generation from an internal reference. When the processor exits reset, it
performs the following:
• Reads the start SP (SP_main) from vector-table offset 0
• Reads the start PC from vector-table offset 4
• LR is set to 0xFFFF_FFFF
The on-chip peripheral modules are disabled and the non-analog I/O pins are initially
configured as disabled. The pins with analog functions assigned to them default to their
analog function after reset.
During and following a reset, the SWD pins have their associated input pins configured
as:
• SWD_CLK in pull-down (PD)
• SWD_DIO in pull-up (PU)
6.2.2.1 External pin reset (RESET)
This pin is open drain and has an internal pullup device. Asserting RESET wakes the
device from any mode.
The RESET pin can be disabled by programming RESET_PIN_CFG option bit to 0.
When this option selected, there could be a short period of contention during a POR ramp
where the device drives the pin out low prior to establishing the setting of this option and
releasing the RESET function on the pin.
Reset
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
128 Freescale Semiconductor, Inc.
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