NXP Semiconductors KL25 Series - Configuration (Tpmx_Conf)

TPMx_STATUS field descriptions (continued)
Field Description
2
CH2F
Channel 2 Flag
See the register description.
0 No channel event has occurred.
1 A channel event has occurred.
1
CH1F
Channel 1 Flag
See the register description.
0 No channel event has occurred.
1 A channel event has occurred.
0
CH0F
Channel 0 Flag
See the register description.
0 No channel event has occurred.
1 A channel event has occurred.
31.3.7 Configuration (TPMx_CONF)
This register selects the behavior in debug and wait modes and the use of an external
global time base.
Address: Base address + 84h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
TRGSEL
0
CROT
CSOO
CSOT
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
GTBEEN
0
DBGMODE
DOZEEN
0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TPMx_CONF field descriptions
Field Description
31–28
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
Table continues on the next page...
Chapter 31 Timer/PWM Module (TPM)
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Freescale Semiconductor, Inc. 559