NXP Semiconductors KL25 Series - Register Definition

M
PE
PT
RE
VARIABLE 12-BIT RECEIVE
STOP START
RECEIVE
WAKEUP
DATA BUFFER
INTERNAL BUS
SBR12:0
BAUDRATE
CLOCK
RAF
LOGIC
SHIFT DIRECTION
ACTIVE EDGE
DETECT
LBKDE
MSBF
GENERATOR
SHIFT REGISTER
M10
RXINV
IRQ / DMA
LOGIC
DMA Requests
IRQ Requests
PARITY
LOGIC
CONTROL
RxD
RxD
LOOPS
RSRC
From Transmitter
RECEIVER
SOURCE
CONTROL
BAUD
Figure 39-2. UART receiver block diagram
39.2 Register definition
The UART includes registers to control baud rate, select UART options, report UART
status, and for transmit/receive data. Accesses to address outside the valid memory map
will generate a bus error.
UART memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4006_A000 UART Baud Rate Register High (UART0_BDH) 8 R/W 00h 39.2.1/725
4006_A001 UART Baud Rate Register Low (UART0_BDL) 8 R/W 04h 39.2.2/726
4006_A002 UART Control Register 1 (UART0_C1) 8 R/W 00h 39.2.3/726
4006_A003 UART Control Register 2 (UART0_C2) 8 R/W 00h 39.2.4/728
4006_A004 UART Status Register 1 (UART0_S1) 8 R/W C0h 39.2.5/729
Table continues on the next page...
Register definition
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
724 Freescale Semiconductor, Inc.