NXP Semiconductors KL25 Series - Master Mode

The clock phase control bit (CPHA) and clock polarity control bit (CPOL) in the SPI
Control Register 1 (SPIx_C1) select one of four possible clock formats to be used by the
SPI system. The CPOL bit simply selects a non-inverted or inverted clock. The CPHA bit
is used to accommodate two fundamentally different protocols by sampling data on odd
numbered SPSCK edges or on even numbered SPSCK edges.
The SPI can be configured to operate as a master or as a slave. When the MSTR bit in
SPI Control Register 1 is set, master mode is selected; when the MSTR bit is clear, slave
mode is selected.
37.4.2 Master Mode
The SPI operates in master mode when the MSTR bit is set. Only a master SPI module
can initiate transmissions. A transmission begins by reading the SPIx_S register while
SPTEF = 1 and writing to the master SPI data registers. If the shift register is empty, the
byte immediately transfers to the shift register. The data begins shifting out on the MOSI
pin under the control of the serial clock.
• SPSCK
• The SPR3, SPR2, SPR1, and SPR0 baud rate selection bits in conjunction with
the SPPR2, SPPR1, and SPPR0 baud rate preselection bits in the SPI Baud Rate
register control the baud rate generator and determine the speed of the
transmission. The SPSCK pin is the SPI clock output. Through the SPSCK pin,
the baud rate generator of the master controls the shift register of the slave
peripheral.
• MOSI, MISO pin
• In master mode, the function of the serial data output pin (MOSI) and the serial
data input pin (MISO) is determined by the SPC0 and BIDIROE control bits.
•
SS pin
• If MODFEN and SSOE bit are set, the SS pin is configured as slave select
output. The SS output becomes low during each transmission and is high when
the SPI is in idle state. If MODFEN is set and SSOE is cleared, the SS pin is
configured as input for detecting mode fault error. If the SS input becomes low
this indicates a mode fault error where another master tries to drive the MOSI
and SPSCK lines. In this case, the SPI immediately switches to slave mode by
clearing the MSTR bit and also disables the slave output buffer MISO (or SISO
in bidirectional mode). As a result, all outputs are disabled, and SPSCK, MOSI
and MISO are inputs. If a transmission is in progress when the mode fault
occurs, the transmission is aborted and the SPI is forced into idle state. This
Chapter 37 Serial Peripheral Interface (SPI)
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Freescale Semiconductor, Inc. 669