NXP Semiconductors KL25 Series - Modes of Operation

24.1.2 Modes of Operation
The MCG has the following modes of operation: FEI, FEE, FBI, FBE, PBE, PEE, BLPI,
BLPE, and Stop. For details, see MCG modes of operation.
24.2 External Signal Description
There are no MCG signals that connect off chip.
24.3 Memory Map/Register Definition
This section includes the memory map and register definition.
The MCG registers can only be written when in supervisor mode. Write accesses when in
user mode will result in a bus error. Read accesses may be performed in both supervisor
and user mode.
MCG memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4006_4000 MCG Control 1 Register (MCG_C1) 8 R/W 04h 24.3.1/372
4006_4001 MCG Control 2 Register (MCG_C2) 8 R/W 80h 24.3.2/373
4006_4002 MCG Control 3 Register (MCG_C3) 8 R/W Undefined 24.3.3/374
4006_4003 MCG Control 4 Register (MCG_C4) 8 R/W Undefined 24.3.4/374
4006_4004 MCG Control 5 Register (MCG_C5) 8 R/W 00h 24.3.5/376
4006_4005 MCG Control 6 Register (MCG_C6) 8 R/W 00h 24.3.6/377
4006_4006 MCG Status Register (MCG_S) 8 R 10h 24.3.7/378
4006_4008 MCG Status and Control Register (MCG_SC) 8 R/W 02h 24.3.8/380
4006_400A
MCG Auto Trim Compare Value High Register
(MCG_ATCVH)
8 R/W 00h 24.3.9/381
4006_400B
MCG Auto Trim Compare Value Low Register
(MCG_ATCVL)
8 R/W 00h 24.3.10/381
4006_400C MCG Control 7 Register (MCG_C7) 8 R/W 00h 24.3.11/382
4006_400D MCG Control 8 Register (MCG_C8) 8 R/W 80h 24.3.12/382
4006_400E MCG Control 9 Register (MCG_C9) 8 R/W 00h 24.3.13/383
4006_400F MCG Control 10 Register (MCG_C10) 8 R/W 00h 24.3.14/383
Chapter 24 Multipurpose Clock Generator (MCG)
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Freescale Semiconductor, Inc. 371